1. Technical Field
The invention is related to a modem having an application specific integrated circuit (ASIC) controlled by a digital signal processor (DSP) which receives interrupt requests from the ASIC.
2. Background Art
Modulator-demodulator (modem) circuits commonly used in personal computers to interface with a telephone line can be implemented with a DSP, which performs the processing tasks, a memory, and an ASIC which provides data transfer between the DSP and the main bus of the personal computer. The ASIC consists of a number of modules and sub-modules, each of which can assert an interrupt request to the DSP, so that at any one time there may be several interrupt requests pending for the DSP to service. In order to service a particular one of the pending interrupt requests, the DSP must (1) determine which one of the modules or sub-modules in the ASIC was the source of the interrupt request, and then (2) determine the location in the memory of the appropriate interrupt service routine (ISR) for servicing an interrupt request of that particular module or sub-module. These two determinations which the DSP must make require a certain amount of time and therefore increase the interrupt servicing latency, a significant problem.
The foregoing limitations are overcome in the present invention by having the ASIC itself automatically provide the DSP with a vector pointing to the memory location of the interrupt service routine for the currently pending interrupt request having the highest priority of all pending requests. The DSP reads this vector and uses it to access the interrupt service routine in the memory. Reading of this vector causes the interrupt request to be de-asserted, which causes the next highest priority pending interrupt request to become the highest priority pending interrupt request. As a result, a new vector is presented for the next read by the DSP, and the cycle continues.
In a preferred embodiment, a modem includes a DSP, an ASIC which generates N interrupt requests to be serviced by the DSP, a memory accessible by the DSP and containing at respective address locations therein individual interrupt services routines to be executed by the DSP in servicing respective ones of the interrupt requests, and a DSP bus connected to the DSP, the ASIC and the memory. An interrupt request status register (ICSR) is connected to receive the N interrupt requests and has N flags corresponding to respective ones of the N interrupt requests which reflect their pending status (or lack thereof). The flags are associated with respective numbers according to a priority ranking of the interrupt requests. A look-up table stores, by the respective numbers, vectors corresponding to the respective address locations, the look-up table having a look-up table input and a look-up table output providing a vector corresponding to a number received at the look-up table input. An interrupt control vector register (ICVR) is connected to the look-up table output and is read by the DSP, so that the ICVR contains a vector provided by the look-up table output. A controller has a controller input connected to the ICSR and a controller output specifying the respective number of the highest priority pending flag in the ICSR, the output being coupled to the look-up table input. The controller changes the status of a pending flag in the ICSR upon the DSP reading the corresponding vector in the ICVR, whereby the contents of the ICVR is updated to reflect the current highest priority pending interrupt request.
Preferably, the look-up table further contains a null vector. The controller specifies the null vector to the look-up table input whenever none of the N interrupt requests is pending. As a result, the ICVR contains the null vector in the absence of pending interrupt requests.
The ICSR, the ICVR, the look-up table and the controller preferably are within the ASIC.